Synchronizing system for refresh memory

ABSTRACT

A recirculating refresh memory comprising dynamic shift registers provides character codes in sequence to a character generator, which in turn draws the characters on a cathode ray tube display screen. The memory output is stepped from one character to the next at either fixed or variable time intervals, depending on the position of the memory in its refresh cycle and the occurrence of sync pulses from the AC line. The sync pulses may be referenced to any point in the memory and are allowed to move relative to text stored in memory.

United States Patent [1 1 Blejwas, Jr. et a1.

[ 51 Dec. 30, 1975 Assignee: Vydec, lnc., Whippany, NJ.

Filed: May 6, 1974 Appl. No.: 467,270

6/1973 Rosenthal 340/324 A 1/1974 Puckett et a1...; 340/324 A PrimaryExaminerDavid L. Trafton Attorney, Agent, or Firm-Stephen P. Fox

57 ABSTRACT A recirculating refresh memory comprising dynamic shiftregisters provides character codes in sequence to a character generator,which in turn draws the characters on a cathode ray tube display screen.The memory output is stepped from one character to the next [52] U.S.C1 1. 340/324 A' 328/72 51 Int. cl. Gti6F 3/14 at either fixed orvariable time intervals, depending en 58 Field of Search 340/324 A;328/72, 229 the Position of the memory in its refresh eyele and theoccurrence of sync pulses from the AC line. The sync 5 References Citedpulses may be referenced to any point in the memory UNITED STATESPATENTS gplmzie allowed to move relative to text stored in 3,548,40212/1970 Schumacher 340/324 A y. 3,598,911 8/1971 Helbig 340/324 AD 10Claims, 6 Drawing Figures (1 3 /5 REFRHH uuacrsx c RT MEMORY QENERIIOEDISPLAY Rsouesr I9 ,7 ZZZ/22y NEXT CRAB Na cons:

E55" 1y: cwcx Mrnonv A a7 39 4s 4s 41 1 J *5 M 52222 JSZNTEQ 355,11, K eEsssr A: L f 50 o J 9i i Q; as K 5, J 3f K 52 JL (in 53 mix \35 $v-cPULSE Ems: DEYECW ,25 ZERO (BQBINQ DETECYOE AC1 um:

Vou'AqE US. Patent Dec. 30, 1975 Sheet 1 of3 REFRESH (uAkAcrEk c RTMEMORY qsmmroe DISPLAY Rmuesr 9 7 6TEP NEXT CHAR- l I Nap c0055 MEMORY45 5727; fl BW- 575 l 5 (LOCK 2; 23 RESET 7 2, Aowesss r 45 4a 47 J Q200 77s DELAY MA x- Tmx CLOCK COUNTER S Q K P I j RESET OR o r 35 J @I$2 K 4 P 3 K 92-. I L J'L CLK 29 53 L 63 SYNc PULSE" EDGE asrscrog ZERO(EQiSINc- DETECTOR AC. LINE VOLTAGE U.S. Patent Dec.30, 1975 YES.

STE 327 SYNCI-IRONIZING SYSTEM FOR REFRESH MEMORY CROSS-REFERENCES TORELATED PATENTS AND APPLICATIONS The present application relates to U.S.Pat. No. 3,660,833, and copending U.S. Pat. application Ser. No.464,990, filed Apr. 29, 1974 in the names of Patrick P. de Cavaignac andPeter D. Dickinson.

BACKGROUND OF THE INVENTION A The present invention relates generally toa system in which information contained in a recirculating refreshmemory is repeatedly applied to a display device such as a cathode raytube. More particularly, the invention relates to a method and apparatusfor synchronizing the refresh memory with periodically recurringsynchronization signals, derived from an AC power line for example.

The display of a page of alphanumeric characters on a CRT screen isaccomplished by moving an electron beam across the phosphor surfaceinside the tube. The beam is magnetically or electrostatically directedto each character position on the screen and then controlled to producethe des red character shapes. The beam energizes the phosphor which inturn emits light, but the light diminishes rapidly and the charactersfade in a fraction of a second. To sustain the image, the characters onthe screen must be drawn repetitively, thereby to refresh" the display.In order to prevent the display from flickering to the eye of anobserver, the refresh should occur at least 40 times per second.

Since the electron beam is directed by magnetic or electrostatic fields,it can be misdirected if influenced by unwanted interference fields.Such interfering fields are most commonly caused by the alternating linecurrent which supplies the electrical power to the equipment. Thedisturbances are alternating ones. They change cyclically at theconstant line frequency of 60 cycles per second. Thus character jitterwill occur at the rateof 60 times per second.

If a page of characters on the CRT screen is refreshed at a ratedifferent than the AC line frequency, say 40 times per second, thecharacter signals and the disturbance signals will shift with respect toeach other with each refresh. The effect is that the display will appearto wobble at a rate equal to the difference between the line frequencyand the refresh frequency, namely cycles per second. A wobbling displaysoon becomes unpleasant and annoying to an observer. Elimination of mostof the wobble can be achieved by making the refresh rate the same as theline frequency, i.e., 60 cycles per second. In this case, the displayrefresh is synchronized to the power line frequency. Typically, eachrefresh cycle is initiated by a trigger pulse derived from the powerline.

Most schemes for drawing characters on a CRT screen have the commoncharacteristic that each character is allotted the same drawing time asall others, regardless of character complexity. The average drawing timeper character is largely a function of the most difficult andtime-consuming characters to draw. Thus, a complex number 8 will begiven the same drawing time as aperiod The refresh memory is steppedfrom character to character at a constant speed. This type of systemlimits the total number of characters that can be drawn during eachrefresh cycle, which is 1/60 of a second long. One way to increase thenumber of characters drawn is to lengthen the time of each refresh cycleto 1/40 of a second for example, but the consequence is a wobblydisplay, as described above.

Another way to increase the number of characters displayed is to allotdifferent drawing times to the characters depending on their complexity,as described in U.S. Pat. No. 3,660,833, issued May 2, 1972 and assignedto the same assignee as the present invention. With this technique, thetime given to draw an 8 is much greater than that for a period. Therefresh memory is stepped at a slower speed for complex characters thanit is for simple characters. The problem with this technique is thatmemory stepping is not constant. The refresh memory does not operate ata constant 60 cycle per second refresh rate, and synchronism with thepower line may be lost and the display may wobble.

One way to preserve synchronism when memory clocking is not constant isto structure the refresh memory with a sequential array of static shiftregisters. These devices may be clocked at any rate from zero to theirdesign maximum. Thus, when the drawing of a page of text on the CRTscreen has been completed, the refresh memory can remain static untilthe next power line synchronizing pulse is received. The disadvantage ofstatic shift registers is that they are more expensive and require morecomplex circuitry than dynamic shift registers. For these reasons, it isdesirable to structure the refresh memory with dynamic shift registers;however, such registers must be continually clocked at some specifiedminimum rate to prevent them from losing information. Thus, it is notpossible to delay clocking of a dynamic shift register memory until asynchronization pulse arrives.

SUMMARY OF THE lNVENTION The present invention provides a synchronizingsystem which permits characters to be drawn at different rates on a CRTscreen using non-constant clocking of a refresh memory which comprisesdynamic shift registers. The characters displayed on the screen aresubstantially flicker-free and do not wobble. The number of charactersper page that can be displayed is substantially larger than with othersystems employing constant character drawing times, yet the circuitryrequired is relatively inexpensive and not complex. The quality of thecharacters displayed is as good or better than other systems.

According to the illustrated embodiment of the in vention, there isprovided floating reference" syn chronizaion of the refresh memory andthe power line frequency. Synchronizing pulses derived from the powerline may be referenced to any point in the memory rather than only to afixed point. The beginning of each refresh cycle is varied relative tothe beginning of each cycle of the AC power line. The variations in thesync pulse reference point depend on the time needed to draw all of thecharacters on the display screen in each refresh pass.

During a refresh cycle, the memory may be stepped from character tocharacter at threedifferent clock rates: (1) a fixed slow rate whichtakes longer than the drawing time for the most complex character to bedisplayed; (2) a varying rate which depends on the time required for theCRT beam to draw each character; and (3) a fixed fast rate which stepsthe' memory quickly through unused memory locations and which isgenerally too short in time to permit drawing of characters. Thecharacter-by-character drawing of each page displayed is started bystepping the refresh memory at the slow clock rate. This continues untila power line synchronizing pulse is received. Thereafter, the memory isstepped at a variable clock rate as determined by the complexity of thecharacters themselves until all the characters on the page are drawn bythe CRT beam. From then on, the memory is stepped at the fast clock rateuntil it reaches the beginning character of the page. The three clockrates are used in a manner such that the total clocking time spent perpage of characters displayed on the CRT screen will equal the refreshperiod of 1/60 second. When all the characters in memory cannot be drawnin this time, the slow clock rate is not used, and instead the memory isstepped as fast as possible after each character is drawn.

In effect, the slow clock rate is used to fill in unused refresh time,thereby to provide the timing adjustment for variations in text. Ascharacters are added in the refresh memory, more time is spent indrawing them and the number of slow memory clock pulses produced duringeach refresh cycle will automatically be reduced. Conversely, whencharacters are removed from the memory, more fill-in time is requiredand thus more slow clock pulses are used.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of thepreferred embodiment of the system incorporating the present invention.

FIGS. 2 (a)-(c) are waveform diagrams illustrating the generation ofsynchronization pulses.

FIG. 3 is a flow diagram illustrating the operation of the system ofFIG. 1.

FIG. 4 is a timing diagram illustrating one mode of operation of thesystem of FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG. 1, arefresh memory 11 provides characters to a character generator 13, whichin turn controls a cathode ray tube (CRT) display 15 to drawalphanumeric characters on the CRT screen. Refresh memory 11 comprises aplurality of dynamic shift registers in a recirculating loop. Charactersare stored in coded form and applied one-by-one to character generator13. Memory 11 has a character capacity large enough to produce a page oftext on the CRT screen. With each circulation of the memory, the page oftext is refreshed on the CRT screen. Memory 11 is stepped from onecharacter location to the next by a STRT signal at its control input 17.After a character at the memory output is drawn on the CRT screen bycharacter generator 13, it produces a Request Next Character pulse onoutput line 19. This pulse occurs at the end of each character andremains high until the memory is stepped to the next character. Memoryorganization is such that any unused memory locations at the end of thememory following a page of text contain special NOP codes. These codesare recognized by character generator 13 to maintain the signal atoutput line 19 high, as shown in FIG. 1.

A memory address counter 21 is incremented one count by the STRT pulseeach time memory 11 is stepped to its next character location. Anaddress decoder 23 produces an output signal A,, when the count incounter 21 indicates that the first character location in thecirculating memory 11 has been reached. In operation, the A pulse occursat the beginning of each 4 refresh cycle and at that. time counter 21 isreset by means not shown to begin the count for the next refresh cycle.

The configuration and operation of the character generator and CRTdisplay system is described in more detail in U.S. Pat. No. 3,660,833issued to Walter T. Blejwas et al on May 2, 1972 and in copending US.Pat. application Ser. No. 464,990, entitled Cursor Find System For theDisplay of a Word Processing System," filed in the names of Patrick P.de Cavaignac and Peter D. Dickinson. Said patent and application areassigned to the same assignee as the present invention.

The system of FIG. 1 also includes a first detector 25 which receives ACline voltage and detects the zero crossover point thereof. The AC linevoltage is shown in FIG. 2(a). The output of detector 25 is a squarewave signal, as shown in FIG. 2(b). Each edge of this signal representsa cross-over point and the positive going edges are detected by a seconddetector 27 which produces a synchronization pulse in response thereto,as shown in FIG. 2(0). The AC line operates at 60 Hertz so the timebetween synchronization pulses is 16.7 milliseconds (ms). Each syncpulse is 200 nanoseconds (ns) long.

Refresh memory 11 is not stepped from character to character at aconstant clock rate throughout each refresh cycle. Instead, memoryclocking varies and depends on the text displayed and the occurrence ofa sync pulse generated from the AC line voltage. As will be described indetail hereinafter, the sync pulse may be referenced to any point in thememory and allowed to move as a function of the text displayed. Hence,this system is referred to as floating reference synchronization.

The system operates to step refresh memory 11 in three different ways:(I) at a predetermined slow rate wherein the period between clocking(STRT) pulses is T (2) at a variable rate dependent on the time requiredfor the CRT'beam to draw each particular character; and (3) at apredetermined fast rate which serves to move the memory quickly throughunused memory locations that contain no text. In general, the systemwill remain sychronized to the AC line if the following boundaryequations are satisfied:

EQUATION l N T T,

EQUATION 2 N T, T,

Where N is the number of characters that may be stored in memory 11, Tis the maximum memory clock period used; T, is the time between syncpulses; and T, is the time spent at each character location on the CRTscreen. For example, with a 60 Hertz line frequency and a memory withcapacity N 2048 characters, the time T is 40 microseconds, T, is 16.7milliseconds, and T varies from I microsecond for unused (NOP) characterlocations to 40 microseconds (T,,,,,,) for complex characters, with anaverage of 5- microseconds.

The circuitry that maintains the non-constant memory steppingsynchronized with the AC line is shown in FIG. 1 and the operationthereof is illustrated by the flow diagram of FIG. 3. Assume that memory11 is beginning a refresh cycle and that the initial address pulse A hasjust been produced. The A,, pulse is applied to the J input of a J-Kflip-flop 29, thereby to set this flip-flop. Assume also that aflip-flop 23 is initially in its reset state so its Q output is high.The Q and Q signals enable an AND gate 35, which in turn conditions anAND gate 37 to be enabled by the memory clocking signal STRT. At thistime, the system is in state A, indicated by block 301 in FIG. 3. The Q-Q designation adjacent block 301 illustrates the condition offlip-flops 29, 33, respectively, in FIG. 1.

Initially, memory 11 is stepped at fixed slow speed at intervals T (4Omicroseconds, for example). This is achieved as follows: the STRT pulseat the beginning of the refresh cycle enables AND gate 37, the output ofwhich is applied to the J input of a J-K flip-flop 39, thereby to setthis flip-flop. As a result, the Q output thereof goes low. The STRTsignal is also applied through an OR gate 41 to the reset input of acounter 43. Thereafter, counter 43 counts pulses (at 200 nanosecondintervals, for example) from a clock 45. A de coder 47 monitors theoutput of counter 43 and produces an output pulse when the contents ofcounter 43 reaches a count indicating that the time interval T haselapsed. The output pulse from decoder 47 is ap plied to the K input offlip-flop 39, thereby to reset it and cause the Q output thereof to gohigh. This Q output is applied to an AND gate 49 along with the output19 of character generator 13 that is held high after a character iscompleted. Thus, after the delay T occurs, the next pulse from a clock51 enables AND gate 49 to produce STRT which steps the memory to thenext character location. Clock 51 produces pulses at l microsecondintervals, for example, and is reset by each STRT pulse to keep itsynchronized with the rest of the system. The STRT pulse also advancescounter 21, resets delay counter 43 and sets flip-flop 39, thereby tostart the entire T delay cycle over again.

The above-described operation is shown in FIG. 3, beginning at state A(block 301). Thereafter, a STRT signal is produced (block 303) and the Tdelay is monitored (by flip-flop 39) as indicated by decision block 305.During the T delay interval, the system also monitors for the occurrenceof a sync pulse, as indicated by decision block 307 and as describedlater. As long as no sync pulse occurs, the system waits for completionof delay T after which operation returns to state A. Thus, STRT pulsesare produced at intervals T to step the memory. In this mode ofoperation, memory stepping is constant at T intervals even though eachcharacter is drawn on the CRT screen in substantially less time than TMemory stepping progresses at T intervals until a sync pulse occurs atthe output of detecor 27. In response to the first sync pulse, thefollowing occurs: (1) flip-flop 29 is reset, so the Q output goes low,thereby to disable AND gate which in turn prevents STRT pulses fromsetting flip-flop 39; (2) the Q output of flip-flop 29 goes high tocondition an AND gate 50 to be enabled and set flip-flop 33 in responseto the next sync pulse; and (3) delay counter 43 is reset. The resettingof counter 43 operates to extend the last memory stepping interval so itends exactly T microseconds after the arrival of the sync pulse, therebyto maintain precise synchronization and prevent jitter of the display.When the last T pulse does occur, it resets flip-flop 39, whichthereafter is held in its reset mode because AND gate 37 is disabled asdescribed above and the J input cannot receive STRT pulses. In FIG. 3,the resetting of delay counter 43 is indicated by block 309 andmonitoring for the completion of a full T delay after the sync pulse isindicated by decision block 31 1.

When flip-flop 39 is reset by the last T pulse, the Q output thereofgoes high and the next STRT pulse is produced (block 313 in FIG. 3).Thereafter, the Q output stays high and AND gate 49 produces a STRTpulse in response to a clock pulse from clock 51 as soon as charactergenerator 13 completes drawing one character and provides a high levelsignal on line 19 to request the next character from memory 11. In thismode of operation, a STRT pulse is produced as soon as a character isdrawn and memory 11 is stepped from character to character at a varyingrate, depending on how long it takes to draw each character. In FIG. 3,operation cycles through state B (block 315), producing a STRT pulse tostep the memory (block 317) after each character is drawn, as indicatedby decision block 319. This continues as long as a sync pulse does notoccur (decision block 321) and as long as an A, pulse is not produced toindicate that memory 11 has started the next refresh cycle (decisionblock 323). With each new refresh cycle, operation returns to state A(block 301) and the memory is again stepped at T intervals, as describedabove.

If memory 11 is not filled to capacity, the unused memory locations atthe end of the memory contain special NOP codes which cause charactergenerator output 19 to remain high. STRT pulses are then produced byclock 51 at a fixed fast rate, e.g., at one microsecond intervals. Thus,memory 11 is stepped quickly through unused memory locations to thebeginning of the next refresh cycle.

Occasionally, when the memory used has a large capacity, there are somany characters in memory that the time required to draw all of them islonger than the time between two sync pulses, e.g., longer than 16.7milliseconds for a Hertz AC line. In this case, a second sync pulseoccurs in the same refresh cycle. Equation 2 above is violated andunresolvable hunting of the synchronization circuit may occur. Thisproblem is prevented by allowing the memory stepping to run free for allmemory locations until there is a complete refresh cycle without theoccurrence of a sync pulse. In operation, the second sync pulse enablesAND gate 50 to set flip-flop 33. As a result, the Q output thereof .goeslow and prevents AND gate 35 from being enabled the next time Q goeshigh in response to an A pulse at the beginning of a new memory refreshcycle. As shown in FIG. 3, the second sync pulse causes operation tobranch from decision block 321 to state D (block 325). Thereafter, thememory continues to be stepped in response to STRT pulses (block 327)after each character is drawn (decision block 329) as long as a newrefresh cycle is not indicated by an A pulse (decision block 331).

When A, occurs and the next refresh cycle begins, flip-flop 29 (FIG. 1)is set but operation does not return to state A (block 301) because STRTpulses are still prevented from setting flip-flop 39. Thus, at thebeginning of the refresh cycle, the memory is not stepped at the longertime intervals T Rather, memory 11 continues to be stepped as soon aseach character is drawn. This reduces the total refresh cycle time andin effect permits the memory cycle to catch up with the the sync pulses.In FIG. 3, this operation at the beginning of a refresh cycle starts atstate E (block 333). The memory is stepped by STRT pulses (block 335)after each character is completed (decision block 337) until a newrefresh cycle begins (decision block 339), unless in the meantime a syncpulse occurs (decision block 341), in which case operation branches backto state D (block 325). Operation through states D and E insure that thememory is stepped as fast as possible until one complete refresh cycletakes place without the occurrence of a sync pulse. With reference toFIG. 1, the first A, pulse sets flip-flop 29, which in turn conditionsan AND gate 53 to be enabled by the second A pulse, providing nointermediate sync pulse occurs to reset flip-flop 29. When thiscondition is met, AND gate 53 resets flip-flop 33, so its Q goes high,operation branches from decision block 339 back to state A (FIG. 3) andthe above-described memory stepping at T intervals resumes.

Operation of the syncing system in the steady state is defined by thefollowing equation:

EQUATION 3 X maz av s Where X is the number of memory locations,starting at A, to use T clocking time, T is the maximum memory clockperiod used; N is the number of characters that may be stored in memory;T,,,, is the average time per character required to step through allcharacters and unused memory locations (NOPs) on a page of text; and T,is the time between sync pulses. As the quantity of text increases, thenumber of NOPs decreases and T,,,, becomes larger. This forces the firstterm in Equation 3 to reduce in magnitude, and X is therefore reduced (Tis a fixed value). Conversely, when text is removed, T reduces andcauses a corresponding increase in the value of X.

FIG. 4 illustrates the STRT pulses which step memory 11 as a function oftime. The mode of operation shown is that in which only one sync pulseoccurs in each refresh cycle. The beginnings of successive refreshcycles are designated A5, A A etc. The sync pulses that occur during therefresh cycles are designated Sync Sync Sync etc. As shown, memorystepping takes place at fixed intervals T,,,,, until a sync pulseoccurs. Thereafter, the memory is stepped as soon as each character isdrawn on the display until a new refresh cycle begins.

FIG. 4 also illustrates how the synchronizing system adapts in responseto the sudden insertion of additional characters into memory 1 1, as mayoccur during a text editing operation for example. Assume that a blockof 100 characters is suddenly added to memory during the second refreshcycle, i.e., between A and A If the average per-character drawing time Tis 5 microsecond (us), the minimum memory clocking interval is lmicrosecond (us), the total increase in character drawing time is 100 X(5 us 1 us) 400 us. As a result, the starting point of the next refreshcycle is delayed by 400 ,us. If T is 40 us, there will be 400/4O fewer Tintervals produced than the initial number X by the time the next syncpulse (Sync arrives. In FIG. 4, this reduction is indicated as (X l0) TThe 10 characters originally drawn at T intervals are now drawn at theaverage intervals of T 5 us each. Hence, the disturbance has beenreduced to 50 us, the time required to draw the 10 characters (10 X 5 us50 us). The following equation governs the response of the system to adisturbance caused by the insertion of additional characters in memory:

EQUATION 4 n u-1) au utor) Where D is the disturbance time n refreshcycles after the initial disturbance when n 0. In the example givenabove, the disturbance after the first refresh cycle is D,=(400 .ts)(5,us/40,u.s)=50 ,us. After the second refresh cycle, the disturbance D(SOas) (5 us/40us) =6.25 ,us. The system stabilizes as soon as thedisturbance time becomes less than the interval Tmax. Hence, in thiscase, the system will stabilize after the second refresh cycle.

We claim:

1. In a system for producing characters of a page of text on a displayfrom a dynamic recirculating refresh memory, a method for synchronizingthe system to the power line frequency to prevent movement of thedisplay, the method comprising:

stepping said refresh memory from character to character at apredetermined slow clock rate until a power line synchronizing pulseoccurs, wherein the time interval T between each clock pulse is longerthan the time required to produce the most complex character to bedisplayed; and

stepping said refresh memory at variable clock rates after saidsynchronizing pulse occurs until all characters of a page are producedon the display, wherein a clock pulse occurs in response to thecompletion of each character displayed.

2. The method of claim 1, further including:

stepping said refresh memory at a predetermined fast clock rate afterthe last character of a page is produced and until the beginning of thenext refresh cycle of the memory.

3. The method of claim 2, wherein the time interval between each clockpulse of the fast clock rate is at least as short as the time requiredto produce the simplest character to be displayed.

4. The method of claim 1, wherein the stepping of said refresh memory ata predetermined slow clock rate includes:

extending the memory stepping time interval in which said synchronizingpulse occurs so that said interval ends at a time T after saidsynchronizing pulse, thereby to prevent jitter of the display.

5. A synchronizing system comprising:

means for producing periodically recurring sync pulses;

a dynamic recirculating refresh memory for storing a plurality ofcharacters in coded form, said memory having a control input forstepping said memory from one memory location to the next to output thecharacters in sequence;

a character generator coupled to the output of said refresh memory forproducing characters in a manner for display, said character generatorhaving an output indicating when the generation of each character iscomplete;

means for sensing the beginning of each recirculation of said refreshmemory;

first means coupled to the control input of said memory for steppingsaid memory at predetermined long time intervals T which are longer thanthe time required to generate the most complex character to bedisplayed;

second means coupled to the control input of said memory and to saidcharacter generator output for stepping said memory at varying timeintervals in response to the generation of each character; and

control means responsive to said sync pulse producing means and saidsensing means for enabling said first stepping means at the beginning ofa memory refresh cycle and for thereafter disabling said first steppingmeans and enabling said second stepping means when a sync pulse occurs.

6. The system of claim 5, wherein said character generator output alsoindicates unused memory locations and further including third meanscoupled to the control input of said memory and responsive to saidcharacter generator output for stepping said memory at predeterminedshort time intervals when a memory location contains no characterinformation.

7. The system of claim 6, wherein said control means also enables saidthird memory stepping means when a sync pulse occurs.

8. The system of claim 5, wherein said first stepping means has acontrol input coupled to said sync pulse producing means and isresponsive to a sync pulse to 10 extend the next succeeding memorystepping interval to step said memory at time T after the occurrence ofsaid sync pulse.

9. The system of claim 5, wherein said sync pulse producing meansincludes:

means responsive to a source of AC line voltage for detecting the zerocrossover points of said line voltage; and means responsive to said zerocrossover point detector for producing a sync pulse during each cycle ofthe AC line frequency. 10. The system of claim 5, wherein said controlmeans includes:

means responsive to the occurrence ofa second sync pulse in the samememory refresh cycle for holding said first stepping means disabled andsaid second stepping means enabled at the beginning of the next memoryrefresh cycle; and means for disabling said holding means in response tothe absence of a sync pulse during a complete refresh cycle.

1. In a system for producing characters of a page of text on a display from a dynamic recirculating refresh memory, a method for synchronizing the system to the power line frequency to prevent movement of the display, the method comprising: stepping said refresh memory from character to character at a predetermined slow clock rate until a power line synchronizing pulse occurs, wherein the time interval Tmax between each clock pulse is longer than the time required to produce the most complex character to be displayed; and stepping said refresh memory at variable clock rates after said synchronizing pulse occurs until all characters of a page are produced on the display, wherein a clock pulse occurs in response to the completion of each character displayed.
 2. The method of claim 1, further including: stepping said refresh memory at a predetermined fast clock rate after the last character of a page is produced and until the beginning of the Next refresh cycle of the memory.
 3. The method of claim 2, wherein the time interval between each clock pulse of the fast clock rate is at least as short as the time required to produce the simplest character to be displayed.
 4. The method of claim 1, wherein the stepping of said refresh memory at a predetermined slow clock rate includes: extending the memory stepping time interval in which said synchronizing pulse occurs so that said interval ends at a time Tmax after said synchronizing pulse, thereby to prevent jitter of the display.
 5. A synchronizing system comprising: means for producing periodically recurring sync pulses; a dynamic recirculating refresh memory for storing a plurality of characters in coded form, said memory having a control input for stepping said memory from one memory location to the next to output the characters in sequence; a character generator coupled to the output of said refresh memory for producing characters in a manner for display, said character generator having an output indicating when the generation of each character is complete; means for sensing the beginning of each recirculation of said refresh memory; first means coupled to the control input of said memory for stepping said memory at predetermined long time intervals Tmax which are longer than the time required to generate the most complex character to be displayed; second means coupled to the control input of said memory and to said character generator output for stepping said memory at varying time intervals in response to the generation of each character; and control means responsive to said sync pulse producing means and said sensing means for enabling said first stepping means at the beginning of a memory refresh cycle and for thereafter disabling said first stepping means and enabling said second stepping means when a sync pulse occurs.
 6. The system of claim 5, wherein said character generator output also indicates unused memory locations and further including third means coupled to the control input of said memory and responsive to said character generator output for stepping said memory at predetermined short time intervals when a memory location contains no character information.
 7. The system of claim 6, wherein said control means also enables said third memory stepping means when a sync pulse occurs.
 8. The system of claim 5, wherein said first stepping means has a control input coupled to said sync pulse producing means and is responsive to a sync pulse to extend the next succeeding memory stepping interval to step said memory at time Tmax after the occurrence of said sync pulse.
 9. The system of claim 5, wherein said sync pulse producing means includes: means responsive to a source of AC line voltage for detecting the zero crossover points of said line voltage; and means responsive to said zero crossover point detector for producing a sync pulse during each cycle of the AC line frequency.
 10. The system of claim 5, wherein said control means includes: means responsive to the occurrence of a second sync pulse in the same memory refresh cycle for holding said first stepping means disabled and said second stepping means enabled at the beginning of the next memory refresh cycle; and means for disabling said holding means in response to the absence of a sync pulse during a complete refresh cycle. 